1. Field of the Invention
This invention relates to a semiconductor device to be utilized for memory, logic circuit, image sensor etc. and a process for preparing the same. The invention is particularly directed to an SOI (Semiconductor on Insulator) type semiconductor device and a process for preparing the same.
2. Related Background Art
It has been desired to reduce parasitic capacitance in order to make a semiconductor device operate at a higher speed. A device which realizes the higher operating speed and also prevents latch-up to give good radiation resistance, an SOI structure has been well appreciated. On SOI, a semiconductor layer is formed on an insulating substrate, whereby-the parasitic capacitance between the layer and the substrate can be reduced. As an example of the preparation method of SOI, there may be included Silicon on Sapphire (SOS), Separation by Implanted Oxygen (SIMOX), and laser/EB recrystallization methods.
The SOI device prepared according to these methods has attempted to be improved in performances by approximating the crystallinity of the semiconductor layer to that of a single crystal, and there is recently a study to obtain a very high mobility by the mechanism inherent in the device by making the film thickness ultra-thin (e.g. 0.1 .mu.m thickness or less).
However, as one problem which occurs by making the semiconductor ultra-thin, the source and drain regions become also thinner as shown in the equivalent circuit of the transistor shown in FIG. 1. For this reason, the source resistance (R.sub.S), and the drain resistance (R.sub.D) become higher, and the resistance components may sometimes lower the actuation speed of the transistor.
In the prior art, to cope with such problem, there have been proposed, for example, a method in which a thick SOI layer is formed and only the channel portion is subjected to etching, or a method in which after oxidation, the oxidized film is removed, thereby making the channel portion thinner.
There is also a method in which after removal of the gate insulation films at the source and drain portions, films are formed by epitaxial growth so that only the source and drain portions become thick, as disclosed in Japanese Laid-open Patent Application No. 60-20582.
FIG. 2 is a schematic cross-sectional view showing the structure of such prior art example, wherein 1' is a thin channel region, 2' a thick drain region, 3' a thick source region, 4' a gate electrode.
However, in the prior art example, as shown in FIG. 2, after either making the portion corresponding to the channel region 1' thinner or making the portion corresponding to the source region 3' and the drain region 2' thicker, the gate electrode 4' is formed, and with the use of them as the mask, ion-implantation has been effected so as to form the source region 3' and the drain region 2'. For this reason, there is a fear that the portion made thicker so as to form the source and drain regions may be slipped off from the positions where source and drain are actually formed. Therefore, according to this method, it is required to perform registration, and for that purpose, an alignment margin a must be taken. According to the knowledge of the present inventors, the reason why the device of the prior art cannot accomplish sufficient high speed operation is that the semiconductor portion other than source and drain layers remain corresponding to the width of a, which causes parasitic capacitance to be increased.
Also, it has been found that in the upwardly concave structure as in the above-mentioned example of the prior art, an electrical field tends to be concentrated at the corner portions such as b and b', whereby deterioration of the gate insulation film dielectric strength is brought about to cause lowering in reliability.